Low-overhead processor interfacing

ABSTRACT

The present invention relates to a method and system for performing a data transfer between a shared memory ( 16 ) of a processor device ( 10 ) and a circuitry ( 20 ) connected to the processor device ( 10 ), wherein the data transfer is performed by triggering a DMA transfer of the data to the processor device, adding the DMA transfer to a transaction log, and providing the transaction log to the processor device, when the transaction log has reached a predetermined depth limit. The processor device is then informed of the DMA transfer of the transaction log, so as to be able to validate the transferred data. Thereby, significant background data movement can be provided without introducing high core overheads at the processor device ( 10 ).

FIELD OF THE INVENTION

The present invention relates to a method and system for performing adata transfer between a memory of a processor device, such as a digitalsignal processor (DSP), and a circuitry, such as an application specificintegrated circuit (ASIC), connected to the processor device.

BACKGROUND OF THE INVENTION

Distributed memory architectures are very good at implementing data flowprocessing, and data flow processing is in turn what almost every DSPand related application boils down to. Ideal fit between DSP and dataflow systems is further strengthened by the need for DSP application torun in real-time, i.e. they must process data with a specifiedthroughput and/or latency requirement. Shared memory systems may havedifficulties in guaranteeing latency due to the uncertainties overmemory contention.

If the central processing unit (CPU) of a DSP has to stop its currenttask and move data on and off the chip, performance will be poor.Therefore, direct memory access (DMA) controllers are provided forexecuting command sequences, autoinitialization and the like. Inreal-time data processing systems, this allows the DMA to runindependently of the CPU. DMA requires primarily that the DSP does notaccess the memory involved. To achieve this, the CPU may be stopped ordecoupled from the bus system to assure that the CPU and the DMAcontroller are not attempting to access the memories concurrently.During the DMA operation, the addresses fed to the memories are thosegenerated by the DMA controller. After the DMA operation is completed,the addresses generated by the CPU once again determine which memoryword is being accessed. Thus, DMA provides a data transfer which allowsdata to be moved between a peripheral controller and a system memorywithout interaction of the host CPU. The data may be moved by theperipheral controller itself, or by a separate third party DMAcontroller.

The stopping or decoupling of the CPU is usually performed based oninterrupt routines triggered by external circuitries which intend toaccess the shared memory of the DSP. Thus, high interrupt overheads andassociated DSP core load are associated with frequent interrupt serviceroutines (ISRs) triggered in case of data movements between the sharedmemory and external devices or circuitries connected to the DSP.

Document EP 0 908 830 A1 discloses a DSP-based communications adapterincluding a number of digital signal processors and network interfacecircuits for providing an attachment of a multi-channel telephone line.Each digital signal processor interrupts its host processor bytransmitting an interrupt control block as data to a data memory of thehost processor, and by subsequently sending an interrupt causing thehost processor to examine the data memory. Thereby, a number ofinterrupts to the host processor from a single DSP is bundled and can behandled together. The overhead for individually handling each interruptcan thus be reduced. The interrupt blocks are written by means of a DMAoperation to the memory of the host processor.

However, if this prior art solution is used for bundling interrupts ofdata movements between a shared memory of a DSP and an externalcircuitry, the CPU of the DSP still has to handle each interrupt of theinterrupt block in order to trigger the corresponding ISRs required fordata movement. Hence, overhead would still be a problem.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide a methodand system for transferring data between a memory of a processor deviceand a circuitry connected to the processor device, by means of whichinterrupt overheads and associated core load can be reduced.

This object is achieved by a method of performing a data transferbetween a memory of a processor device and a circuitry connected to theprocessor device, said method comprising the steps of:

-   -   setting up a direct memory access (DMA) for transferring data at        said circuitry;    -   triggering a DMA transfer of said data to said processor device;    -   adding said DMA transfer to a transaction log;    -   providing said transaction log to said processor device when        said transaction log has reached a predetermined depth limit;        and    -   informing said processor device of the availability of said        transaction log.

Furthermore, the above object is achieved by a processor device having amemory which can be accessed by a connected circuitry, said processordevice being arranged to validate data, transferred to said memory by adirect memory access, based on a transaction log provided to saidprocessor device.

Additionally, the above object is achieved by an integrated circuithaving means for providing access to a processor device, said integratedcircuit being arranged to set up a direct memory access for transferringdata via said access means, to trigger a DMA transfer of said data, toadd said DMA transfer to said transaction log, to provide saidtransaction log to said processor device when said transaction log hasreached a predetermined depth limit, and to issue an informationindicating the availability of said transaction log.

Moreover, the above object is achieved by a system for performing a datatransfer between a memory of a processor device and a circuitryconnected to said processor device,

wherein said circuitry is arranged to set up a direct memory access fortransferring data, to trigger a DMA transfer of said data to saidprocessor device, to add said DMA transfer to said transaction log, toprovide said transaction log to said processor device when saidtransaction log has reached a predetermined depth limit, and to informsaid processor device of the availability of said transaction log; andwherein said processor device is arranged to validate said transferreddata based on said available transaction log.

Accordingly, a pre-programmed DMA located on interfaces hosted by theexternal circuitry is provided to transfer data between the memory andthe external circuitry, wherein processor control requirements can bereduced by using the transaction log. Thus, a plurality of datatransfers can be bundled with a single DMA operation, since theprocessor device may validate or qualify the transferred data based onthe available transaction log, when the availability, e.g. transfer orinterrogation, of the transaction log has been informed to the processordevice. Since the processor device is only involved in the signaling ofthe information regarding the provision, e.g. transfer or interrogation,of the transaction log, interrupt overheads and associated core load canbe significantly reduced. Furthermore, the need for manual data movementis prevented, and a data rate matching can be provided between theshared memory and the on-chip bus system of the external circuitry tothereby reduced stalling of the system.

Due to the fact that multiple data structures held in the memory can bevalidated using a single processor involvement, e.g. by an interruptservice routine, core processing overhead is reduced especially whencontext switching is required under a real-time operating system (RTOS).Furthermore, since the transaction log can be stored locally within thememory of the processor device, slow core polling of the transactionstatus within the external circuitry is not required. Significantbackground data movements are therefore allowed between the sharedmemory and the external circuitry, because means are provided forsynchronizing and validating the data structures without high coreoverheads.

Preferably, steps b) and c) are repeated until said depth limit has beenreached. Thereby, high amounts of data can be transferred bycorresponding DMA transfers without interrupting the processor device.The DMA transfer may be triggered by hardware or software. Thetransaction log may be configurable or not.

The informing step may be performed by initiating an interruptoperation, e.g. triggering of an interrupt service routine at theprocessor device.

Furthermore, the transaction log may be transferred by an own DMAchannel or may be appended to a data transfer. Alternatively, thetransaction log my be retained in the connected circuitry, forinterrogation following a qualifying interrupt.

BRIEF DESCRIPTION OF THE DRAWINGS

In the following, the present invention will be described in greaterdetail based on a preferred embodiment with reference to the drawingfigures, in which:

FIG. 1 shows a schematic block diagram of a digital signal processorconnected to an ASIC; and

FIG. 2 shows flow diagrams of a data transfer method according to thepreferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The preferred embodiment will now be described based on a pre-programmedDMA located on an ASIC-hosted interface to provide a data movementbetween a shared memory 16 of a DSP or Microcontroller Unit (MCU) 10 andan ASIC 20, as shown in FIG. 1.

According to FIG. 1, the DSP 10 comprises a CPU 12 for controlling DSPoperations based on a control program stored in a program memory (notshown). Furthermore, a host interface 14 is provided for controlling adata transfer to a slave interface 22 arranged at the ASIC 20. Aninterrupt control unit 17 is arranged in the DSP 10 to control theexecution of interrupt service routines based on an interrupt controlsignal received from a resource manager 24 of the ASIC 20. Moreover, aslave interface 18 of the DSP 10 is controlled by a host interface 26 ofthe ASIC 20 so as to transfer data from the ASIC 20 to the shared memory16 of the DSP 10.

In the ASIC 20, a memory 28 is provided for storing data to betransferred e.g. to the shared memory 16. The host interface 26comprises a DMA controller for controlling DMA transfers via the slaveinterface 18 to the shared memory 16. Furthermore, a DMA transactionrecord or log comprising information about a DMA transfer history fromthe ASIC 20 to the DSP is stored at the host interface 26. The resourcemanager 24 is arranged to provide resource control of the ASIC 20 so asto enable the data transfer from the memory 28 to the host interface 26under the control of the DMA controller.

As indicated by the dotted arrows in FIG. 1, a DMA transfer from theASIC 20 to the DSP 10 comprises at least two phases, i.e. a first DMAtransfer DMA #1 for transferring the respective data DATAX to the sharedmemory 16 of the DSP 10 and a directly or later following second DMAtransfer DMA #2 for transferring the DMA transaction log from the hostinterface 26 to the shared memory 16. Thereby, high amounts of data canbe transferred from the memory 28 of the ASIC 20 to the shared memory 16of the DSP 10 by using DMA operations without involving the CPU 12. TheCPU 12 is then informed of the data transfer by an interrupt controlsignal issued from the resource manager 24 to the interrupt control unit17 after the transfer of the DMA transaction log.

An example for a data movement from the ASIC 20 to the DSP 10 is nowdescribed based on the flow diagrams given in FIG. 2.

In an initialization phase the DMA for the transfer of first data DATAXis set up in the ASIC 20 in step S101. Then, a DMA for the transfer ofthe DMA transaction log is also set up in the ASIC 20 in step S102.Thereby, both DMA transfer operations required for the data movementfrom the ASIC 20 to the shared memory 16 of the DSP are initialized.

Then, a run-time DMA handling function is started at the DMA controllerof the ASIC 20 to control the DMA transfer of the required amount ofdata. In step S201, the DMA transfer of the first data DATAX istriggered and an information indicating the transfer of the first dataDATAX is added to the DMA transaction log (step S301). Similarly,subsequent DMA transfers of further data DATAY, DATAZ and DATAA aretriggered in the subsequent steps S202 to S204, while the DMAtransaction log is successively updated in steps S302 to S304. Thus,after the data transfer operation has been completed, the DMAtransaction log contains transfer information specifying the datatransferred to the shared memory 16 of the DSP 10.

When the DMA controller detects that the DMA transaction log has reacheda predetermined depth limit, a transfer notification procedure isinitiated by step S401. Then, a DMA transfer of the DMA transaction logis triggered in step S402 to transfer the DMA transaction log to the DSP10 and store it in the shared memory 16. Then, the DMA controllertriggers an interrupt to the CPU 12 of the DSP 10 by providing acorresponding control information to the resource manager 24 (stepS403). In response to this interrupt, the CPU 12 qualifies or validatesthe data transferred to the shared memory based on the DMA transactionlog also stored in the shared memory 16 (step S404). To achieve this,the interrupt control information supplied from the resource manager 24to the interrupt control unit 17 may comprise a corresponding addressinformation indicating the address of the DMA transaction log. The DMAtransaction log may then comprise an information indicating the addressranges of the transferred data. The completion of the DMA movement inthe transaction log may be indicated using DMA channel numbers

The proposed processor interfacing concept thus allows significantbackground data movement between the ASIC 20 and the shared memory 16without introducing high core overheads at the DSP 10.

It is noted that the present invention is not restricted to thepreferred embodiment described above, but can be used for any DMAtransfer between processor devices and other circuitries connected tothe processor device. Furthermore, the signaling of the DMA transactionlog to the DSP 10 may be performed by any signaling option and is notrestricted to an interrupt operation. The DMA transfer may be performedto and from any memory-mapped location on the ASIC 20 or any othercircuitry connected to the DSP 10. The transfer of the transaction logdoes not necessarily need its own DMA channel (e.g. DMA#2 in FIG. 1). Itmay be appended to a data transfer or may even by retained within theASIC 20 for interrogation following a qualifying interrupt. This mayinclude Interrupt Status. Thus, in FIG. 1, the DMA#2 is optional. Thetransaction log may be e.g. appended to the next data transfer. The DMAis not necessarily located on the host interface 26 of the ASIC 20, butmay also hang on an ASIC OCB. Furthermore, the interrupt not necessarilyhas to be performed between two devices, but may also be triggeredwithin the DSP 10. Thus, in FIG. 2, steps S102, S402 and S403 areoptional steps for the specific case indicated in the configurationaccording to FIG. 1. The DMA transfer may be triggered also in software.The preferred embodiment may thus vary within the scope of the attachedclaims.

1. A method of performing a data transfer between a memory of aprocessor device and a circuitry connected to said processor device,said method comprising the steps of: a) setting up a direct memoryaccess (DMA) for transferring data at said circuitry; b) triggering aDMA transfer of said data to said processor device; c) adding said DMAtransfer to a transaction log; d) providing said transaction log to saidprocessor device, when said transaction log has reached a predetermineddepth limit; and e) informing said processor device of the availabilityof said transaction log.
 2. A method according to claim 1, wherein saidsteps b) and c) are repeated until said depth limit has been reached. 3.A method according to claim 1, wherein said informing step is performedby initiating an interrupt operation.
 4. A method according to claim 3,wherein said interrupt operation initiates an interrupt service routine.5. A method according to claim 1, further comprising the step ofvalidating said transferred data at said processor device based on saidavailable transaction log.
 6. A method according to claim 1, whereinsaid circuitry is an ASIC.
 7. A method according to claim 1, furthercomprising the step of storing said transaction log in said memory.
 8. Aprocessor device having a memory which can be accessed by a connectedcircuitry, said processor device being arranged to validate data,transferred to said memory by a direct memory access, based on atransaction log provided to said processor device.
 9. A processor deviceaccording to claim 8, wherein said processor device is arranged tovalidate said transferred data in response to an interrupt triggered bysaid connected circuitry.
 10. A processor device according to claim 8,wherein said processor device is a digital signal processor.
 11. Anintegrated circuit having means for providing access to a processordevice, said integrated circuit being arranged to set up a direct memoryaccess (DMA) for transferring data via said access means, to trigger aDMA transfer of said data, to add said DMA transfer to said transactionlog, to provide said transaction log to said processor device when saidtransaction log has reached a predetermined depth limit, and to issue aninformation indicating the availability of said transaction log.
 12. Aintegrated circuit according to claim 11, wherein said integratedcircuit is arranged to issue said information by triggering aninterrupt.
 13. An integrated circuit according to claim 11, wherein saidintegrated circuit is an ASIC.
 14. A system for performing a datatransfer between a memory of a processor device and a circuitryconnected to said processor device, a) wherein said circuitry isarranged to set up a direct memory access (DMA) for transferring data,to trigger a DMA transfer of said data to said processor device, to addsaid DMA transfer to a transaction log, to provide said transaction logto said processor device when said transaction log has reached apredetermined depth limit, and to inform said processor device of theavailability of said transaction log; and b) wherein said processordevice is arranged to validate said transferred data based on saidprovided transaction log.